It takes only one rogue wave to kill a power distribution network in high-speed digital designs. Flat impedance optimization before layout lowers the risk
Power integrity (PI) engineers use target impedance to design power delivery across a broad frequency range. Target impedance is a simple estimate using the maximum allowed ripple divided by the maximum expected current step load. For example, in a field programmable gate array (FPGA) where the max ripple is 60 mV and the max current step load is 5 A, the target impedance (Z) is 12 mΩ
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Optimize Power Distribution 
Source: Spectrum
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